0.150 → 0.140 mm
112 segments adjusted after impedance, mesh and solder-mask comparisons.
Explore signal results16-LAYER MOTHERBOARD / LOCAL EM REVIEW
Open report PDFRouting, with evidence.
Loading saved board and simulation data…
01 / BOARD EXPLORER
Inspect the saved routing
Choose a layer or highlight a net.
Scroll to zoom. Drag to pan.
ACTUAL SAVED GEOMETRYF.Cu · Top
14,988 segments · 3,140 viasTrace/pad view; zone fills omitted. Inspect fabrication geometry in KiCad.
0.150 → 0.300 mm
106 eligible top-layer segments widened after clearance screening.
Explore power results02 / RECORDED FDTD SIMULATIONS
14 retained runsCompare the local EM models
STRAIGHT DIFFERENTIAL COUPON
Impedance across frequency
BeforeAfter90 Ω target
2.5 GHz7.5 GHz
BEFORE83.46 Ω0.150 mm
AFTER87.32 Ω0.140 mm
CHANGE AT SELECTED FREQUENCY+3.86 ΩRecorded 25 MHz frequency steps
Why 0.140 mm?
The selected width balances the two tested solder-mask profiles. At 2.5 GHz the models predict 87.3–94.5 Ω. Fabricator confirmation is needed to set production geometry.
Read these results within their scope
Finite-thickness PEC copper, lossless dielectrics and an ideal adjacent ground plane. Fixtures are included. These local comparisons do not establish whole-channel loss, eye margin or complete rail performance.
Inspect the retained simulation runs
| Run | Width | Solver cells | Timesteps | Final energy |
|---|
03 / RECOVERED SOURCE METADATA
2.028002 mm totalInside the 16-layer board
SELECT A LAYERTop solder mask
0.010 mm · relative permittivity 3.5
- Dielectric
- TU-883
- Dielectric εr
- 3.6
- Outer copper
- 45.001 µm
- Inner copper
- 17 µm
Unknown material loss
Dielectric loss and the manufactured mask profile remain unknown. Zero loss tangents are explicit placeholders in the saved stackup.
Only the original Altium Board6/Data metadata was read for this stack. Original route geometry was not imported.
04 / DESIGN CHECKS
Connectivity is complete. Review remains.
0Unconnected items
218Expected width changes
1,260Reported DRC findings
What the checks establish
Footprints, pad placement, nets and fixed drawings were preserved. The openEMS adjustment changed only the documented trace widths, stackup and project rules. No new copper, drill, edge or thermal findings were added.
The 199-item capped mask-bridge sample changed by 19 added and 19 removed pad-pair warnings on unchanged footprints.
Before fabrication
Resolve retained DRC findings; confirm stackup and mask geometry; verify schematic/net mapping; complete DDR, PCIe and other channel checks; and analyze the entire power system using real loads, component models and thermal/current limits.
112 filled/capped vias require suitable fabrication capability.
Reported DRC categories
| Category | Reported items | Sample scope |
|---|
Counts describe KiCad's reported findings, including capped categories; they are not full violation totals. Download the full DRC record.
Numerical consistency checks
- Largest outgoing-power excess
- 0.173%
- Largest unintended incident common mode
- 0.0182%
- Selected coupon, refined Z grid
- 0.425 Ω change at 2.5 GHz
- Routed cutout, maximum complex reflection change
- 0.0015 before / 0.0068 after
- Power model, refined transverse grid
- 0.91% inductance change at 2.5 GHz
All 14 retained runs reached the −50 dB energy criterion. Deep reflection minima remain mesh-sensitive.
05 / SEVEN-PAGE ENGINEERING REPORT
Download PDFThe results, assumptions and evidence
The page images above are rendered from the delivered PDF. The PDF is the canonical report.
06 / PROJECT RECORD
From placement to local EM review
Fresh routing from the placed source
Configured 3 mil track/space and 18/8 mil vias. Switched to Python 3.12 and native KiCad checks. Retained placement and generated independent routing.
USB pairing and return paths
Rerouted and length-matched the USB receive pair on the top layer. Added 75 ground-return vias in the preceding engineering candidate.
Actual openEMS simulations
Built the official solver, recovered source layer metadata, compared mask and mesh cases, and retained 14 valid runs. Applied 0.140 mm USB and 0.300 mm power widths.
Interactive review and handoff
Packaged the board, report, raw evidence and work records. Prepared this public example review with personal paths and private resource links removed.
CONVERSATION EXCERPTS
The requirements we worked from
Clearly labeled, user-approved images of selected verbatim messages. These are rendered excerpts, not application screenshots or a complete transcript. Progress messages reflect their time. These excerpts predate the user's later approval to publish this example design publicly.
07 / PROJECT HANDOFF
Download reproduction filesTake the work with you
Latest review package
The saved routing candidate, source and preceding board, schematic hierarchy, 14 retained simulations, report, geometry checks and reproduction scripts.
Download final KiCad candidateComplete work records
The seven bundles below contain the design, accepted simulation runs, raw probes, geometry, reproduction code and checks. Earlier routing checkpoints and rejected experiments are retained in the owner's work archive. The latest report governs the results.
Installed runtimes, dependency caches and original routed Altium geometry are excluded.
Engineering reportCanonical seven-page PDFPDFAccepted openEMS resultsFourteen retained runs and validation valuesJSON
FINAL PCB SHA-256
e1e56b13565ad465e78f9d0299741d4061a4c4b8146b64bbc53aa9c314169043